1. Field of Invention
The present invention relates to a high voltage device and a manufacturing method thereof, in particular to such device with reduced on-resistance and a method for manufacturing the device.
2. Description of Related Art
FIG. 1A shows a cross-section view of a prior art double diffused metal oxide semiconductor (DMOS) device which includes: a P-type silicon substrate 11; a first isolation structure 12 defining a device region 100, wherein the isolation structure 12 is formed by, for example, local oxidation of silicon (LOCOS); an N-type well 13 in the substrate 11; a source 14 and a drain 15 in the device region 100; a gate 16 between the source 14 and the drain 15; and a body region 17. FIG. 1B shows a cross-section view of a lateral double diffused metal oxide semiconductor (LDMOS) device which includes: a P-type silicon substrate 11; a first isolation structure 12 defining the device region 100, wherein the isolation structure 12 is formed by, for example, LOCOS; a source 14 and a drain 15 in the device region 100; a gate 16 between the source 14 and the drain 15; and a lateral diffusion drain 18 surrounding the drain 15 and separating the source 14 from the drain 15. Compared with low voltage devices, the prior art high voltage devices have a higher on-resistance (Ron); therefore, in applications requiring high-speed operation, the prior art high voltage devices are less effective.
In view of above, the present invention proposes a high voltage device with reduced Ron and a manufacturing method thereof to overcome the drawback in the prior art, so that the device is more effective in high-speed applications.